Clock and data recovery (CDR) circuits may be implemented to allow a system to generate a clock signal, based on a received data signal that is synchronized with the received data signal. CDR circuits may be implemented using analog or digital components.
The received data signals may include a significant amount of interference causing the data signal to jitter. A clock and data recovery circuit may include a phase detector which may not lock or lock with high amount of jitter on the data signal. If the phase detector is not able to lock on the signal, then any extracted clock signal may be corrupted causing data recovery to be severely impacted.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.